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1G UDP/IP Core testbench failures
by cstathis on Jan 14, 2015 |
cstathis
Posts: 1 Joined: Nov 12, 2014 Last seen: Apr 16, 2015 |
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When ARP v2 is enabled for this core, Vivado finds feedback loops in the sim for me and runs out of iterations. When single-slot ARP is enabled, I get other errors with the top level testbench, starting with test 6 (mac data tx.) Are others experiencing this?
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